Industrial & Military standard SSD

SSD Bad Block Management How does bad block occur? And by what means does the SSD detect and manage bad blocks? What are the problems for the bad block management strategy proposed by the manufacturer? And what kind of management method is more superior? Does disk format lead to loss of the bad block list?  What potential risks may be caused by maintenance of the SSD? This article will help you uncover these secrets. Overview The design concept about bad block management concerns the reliability and efficiency of the SSD. While the bad block management methods offered by some SSD vendors are not always so reasonable, it will cause unexpected bad blocks if some abnormal conditions haven't been considered comprehensively during the product design process. E.g, after testing several SSDs with different controllers, we found that new bad blocks caused by abnormal power failure are very common. When we google “bad blocks by power failure” or similar keywords, we wil...

Before writing this article, we found that performance degradation occasionally happened to the SSD during testing process, and the S.M.A.R.T command was confirmed as the cause of this after study. This is seemingly not critical, however, it may bring serious consequence of losing data packets if the SSD is applied in those critical domains like data acquisition, while of course this bug is correctable, first let us look at the screenshot: S.M.A.R.T Overview   As the short for Self-Monitoring Analysis And Reporting Technology, S.M.A.R.T. can be read from its name with the function of fault alarm. The SSD health condition can be monitored and the parameter values can be fed back to the monitoring software or operation systems, in fact, most parameters are meaningful only for SSD engineers, the end users just need to focus on some key indexes, such as New Bad Blocks, Remaining Life and Erase Count, etc.      S.M.A.R.T information of the SSD can be obtained t...

SSD Problems caused by power failure: Generally power failure would cause 3 main problems to SSD when PC runs. 1. Mapping table might get lost because there is no enough time to update and store it. Usually SSD manufacturers do not provide users with tools to recover mapping table. Thus SSD will become undetectable to host and only method is to return the drive to manufacturer for repairing. And SSD vendors will reproduce the drives by firmware which will get all data on SSD lost. 2. SSD mostly deploy DDR or SDRAM as the cache on board. Once power fails, all data in cache will be lost because both DDR and SDRAM are non-volatile media. And these data have never been transferred into NAND flash yet because R/W speed of DDR is far higher than NAND Flash. However host will consider that data writing has already been finished. In this way power failure causes data loss. 3. Power failure results in new nominal bad blocks. ECC of controller checks 256bit data in row and column, a...

In ITS (Intelligent Transportation Systems), PIS (Passenger Information System) and other embedded in-vehicle application, such as video surveillance, data recorder…usually or sometimes the voltage changes unstably, SSD as embedded memory and storage device when doing data video recording is aggressively affected by the unstable input voltage.   First of all, please let me introduce RBER (Raw-Bit Error Rate), RBER is the Bit Error Rate before ECC (Error Correction Code) performing, reflects the initial reliability of Nand flash. The higher RBER, the less reliability of Nand flash. Then, how Input Voltage Affects the Nand Flash of SSD? Firstly, per 0.3V as a voltage difference in set time, the below graph is 3.3V-3.6V fluctuation. (1) When setting 2.7V - 3.V (standard voltage range of NAND flash), the RBER of NAND flash is 10^(-5.850), which is in normal range. (2) When setting as 3.6V - 3.9V, the RBER begins to increase, reach at 10^(-5.845). (...

Aerospace and Defense storage applications require the highest level of reliability, often operating in harsh environments. The Flash storage devices used in these applications must therefore operate flawlessly while exposed to extreme temperatures and high mechanical shock and vibration loads. SATA Gold finger Connector can’t cater to this challenge!  The Fatal Weakness of SATA Gold finger, reasons: 1. The gold finger adopts flat structure, male connector and female connector contact through the plane, inevitably there will be momentary bad contacts during heavy shock and vibration, and the bad contacts may cause system crash or even damage the SSD due to frequent abnormal power loss. 2. The intense shock may result in   drag and malposition between male and female connectors. The gold finger uses fixed structure with no any buffer design, thus it is likely to be damaged by violent drag causing by intense shock. So we RENICE R-SATA Connector can solve this problem. ...

Temperature test of SSD products includes temp cycling test and temp shock test. Note: “Plenty of frost turns to be water drops in the transition process from low temp to high temp, water drops may easily inflict short circuit on chip pins and thus burn the SSD, therefore, reinforcement and waterproof treatment have to be done to a reliable SSD!!!” A true picture of a tested circuit board with frosting surface under -40°C: Temperature Cycling Test Temp cycling first sets the temperature at -50°C and keep it for 4 hours, then increase the temperature to +90°C and keep it for 4 hours, and after this, lower the temperature to -50°C to finish one cycle and start another cycle, multiple cycles one by one. Industrial grade operation temperature standard is -40°C to +85°C, because temperature deviation is common in temperature cabinets, in order to avoid different test results in client-side causing by the deviation, Renice in-house tests extend the temperature testing range to -50°...

Quick Erase which means full disk logic destruction in a few seconds to get all data in the SSD unreadable is critical in some specific environments of military applications. Generally, there are following different requirements for Quick Erase, and the implementation methods by SSD firmware are different: 1. After the Quick Erase, the disk remains visible in OS and reusable after initialization, just all data are read as 0xFF by Winhex. For this type of Quick Erase, the firmware normally erases AES Encryption Key first and then resumes the mapping table to factory defaults. Erasing Encryption Key is to ensure the data can’t be correctly restored, and resuming the mapping table to factory defaults destructs the mapping connections between physical and logical addresses so that the data in the SSD can’t be correctly read. Notes have to be taken for such Quick Erase: If the SSD receives program commands again or there is data in SDRAM hasn’t been written into NAND F...